Semiconductor manufacturers produce integrated circuits (ICs) or microchips in wafers. FIG. 1a generally illustrates the process of manufacturing ICs from wafers 4. Polished, single crystal wafers 4 are organized into an ordered set 8 of wafer lots 12. The wafer lots 12 are numbered according to the sequence in which the wafers are processed 16. For example, lot 0001 is submitted to wafer processing 16 first, followed by the submission of lot 0002, followed by the submission of lot 0003, etc. The most recent wafer lot submitted to wafer processing 16 is the wafer lot 0012.
However, due to the complex nature inherent in wafer processing 16, the wafer lots 12 are not processed in the same order 8 as they were submitted to wafer processing 16. In “Introduction to Semiconductor Equipment,” Y. Nishi, R. Doering [Ed.] “Handbook of Semiconductor Manufacturing Technology,” New York, Basel: Marcel Dekker, 2000, p. 23ff., incorporated herein by reference, J. Hutcheson states that despite the simple linear process flow typical of most semiconductor manufacturing processes, the “ . . . work-in-progress (WIP) moving through the plant will follow complex paths, crisscrossing back and forth in intricate patterns.”
The complex WIP in wafer processing 16 causes a re-ordering of the wafer lots 12. As FIG. 1a shows, the ordered set 20 of the wafer lots 12 that enter wafer test 24 from wafer processing 16 has a different order than the ordered set 8 of the wafer lots 12 that entered wafer processing 16. Wafer lot 0002 will enter wafer test 24 first, followed by wafer lot 0004, etc., The most recent wafer lot submitted to wafer test is the wafer lot 0009.
Testing of ICs 24 is done using automated test equipment (ATE). These semiconductor testers produce a vast amount of data, as there are typically several dozens or hundreds of particular tests per IC, between hundreds and thousands of microchips on a silicon wafer, and typically several thousand wafers produced per month in an average production facility. Hence, a medium sized semiconductor manufacturer typically maintains a database for the Yield Management System (YMS) software. YMS databases are used for analyzing data, finding correlations, and improving manufacturing yield through subsequent engineering decisions. For each wafer lot 12 in the set 20, IC test data is collected and stored in the YMS database.
The re-ordering or scrambling of the wafer lots 12 poses a significant problem to the analyses of the IC test data collected from the wafer lots 12. Established statistical process control (SPC) methods can not be directly and efficiently applied to IC test data from scrambled wafer lots 20, as these methods require that the order of the measurement data reflects the order of the manufacturing process to be controlled.
In one example, an undesired manufacturing flaw in wafer processing 16 is steadily worsening. The undesired increasing parameter trend has not been detected by inline tests performed during wafer processing 16. An SPC test has been designed to detect the undesired parameter trend. The SPC test detects six test measurements or points in a row steadily increasing or steadily decreasing. The SPC test is applied to the stored IC test data in the YMS database, however the undesired steadily increasing trend is not found. FIGS. 1b and 1c show how the scrambled wafer lots 20 cause the undesired trend to remain undetected.
With combined reference to FIGS. 1a and 1b, the graph 28 (FIG. 1b) illustrates IC test data parameter measurements of the wafer lots 12 (FIG. 1a) plotted 32 (FIG. 1b) according to the ordered set 8 (FIG. 1a) in which the wafer lots 12 (FIG. 1a) were submitted to wafer processing 16 (FIG. 1a). The graph 28 (FIG. 1b) does not have more than 6 test measurements increasing in a row, therefore the undesired trend in wafer processing 16 remains undetected.
With combined reference now to FIGS. 1a and 1c, the graph 36 (FIG. 1b) illustrates parameter measurements of the wafer lots 12 (FIG. 1a) plotted 40 (FIG. 1b) according to the ordered set 20 (FIG. 1a) in which the wafer lots 12 (FIG. 1a) were tested. Again, in graph 36 (FIG. 1b) no more than six test parameter measurements are steadily increasing in a row, and the SPC test fails to detect the flaw in the manufacturing process 16. Applying SPC methods directly and efficiently is critical to maintaining a high yield, which is of utmost importance for the productivity and competitiveness of a semiconductor manufacturer. Hence monitoring IC test data of scrambled wafer lots would be highly desirable.